1. Field of the Invention
The invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having contactless memory arrays.
2. Description of Related Art
Conventionally, as a fabrication method of a semiconductor memory device having contactless memory arrays, the following method has been known (reference to, for example, Japanese Unexamined Patent Publication No. 2001-77220)
In this method, an ONO layer is formed on a substrate, the ONO layer is etched to form a plurality of columns, an impurity is implanted between the neighboring columns to form bit lines, an oxide is grown thermally on the bit lines, and a plurality of rows made of polysilicon or the like are formed on the ONO layer and the bit line oxide so as to cross the columns of the ONO layer.
However, according to the conventional method, it is necessary to carry out a step of thermally growing the oxides on the bit lines after the bit line formation. In the step, therefore, the impurity for forming the bit lines is diffused to make shortening the channel of a transistor difficult.
Further, it is also difficult to form the oxide in a thick layer on the bit lines; thus, it is difficult to suppress a parasitic capacitance between the bit lines and the word lines to be low.